1. Field of the Invention
The present invention relates to a drive circuit for a display device (for example liquid-crystal display device) and in more detail relates to a drive device for a display device whereby miniaturization and reduction of current consumption can be achieved.
2. Description of the Related Art
A drive circuit for a liquid-crystal display device incorporating RAM (Random Access Memory) as a frame memory is commonly employed in liquid-crystal models for mobile telephones. For the drive circuits employed in such applications, miniaturization, reduced current consumption and improved image quality are demanded. It is therefore desired to achieve miniaturization of the liquid-crystal display device as a whole by miniaturizing the drive circuit, to achieve reduction of current consumption by eliminating surplus operations and to achieve improvement in image quality by improving performance.
Typically, the drive circuit for a liquid-crystal display device outputs a plurality of gradation voltages (for example, in the case of 64 gradations, 64 gradation voltages) from a prescribed number of output terminals (for example, in the case where there are three output terminals for R, G and B at each pixel, with a total pixel number=132, the total number of output terminals is 396). In this way, the desired color image is displayed by varying the amount of light transmitted through the liquid-crystal panel for each pixel.
The drive circuit for a liquid-crystal display device includes a gradation voltages output circuit that select a single desired gradation voltage using gradation data from a prescribed number of gradation voltages (in the image data) and output these selected gradation voltages to the various output terminals. It is therefore necessary for the gradation voltages output circuit to amplify (or buffer) the gradation voltages. Two methods of arranging the amplifiers for performing this are conventionally known, namely, “switch drive and “amplifier drive”. “Switch drive” means that the same number of gradation amplifiers as the number of voltage gradations (for example, 64 gradation amplifiers if the number of voltage gradations is 64) is provided for each of the gradations, and a gradation voltage selection circuit that is provided at the output of these gradation amplifiers selects and outputs the desired gradation voltage to each output terminal. The characteristic feature of this method is that the current consumption for output of the gradation voltage is that consumed within the gradation amplifiers, which are provided in the same number (for example 64) as the number of voltage gradations.
In contrast, “amplifier drive” means that respective amplifiers are arranged at all of the plurality of output terminals (for example all of 396 output terminals), and the gradation voltage at each output terminal is amplified (or buffered). In the case of this method, the current consumption for output of the gradation voltage is that consumed within the amplifiers, which are of the same number as the number of output terminals (for example 396).
Thus, comparing the two methods: “switch drive” and “amplifier drive” in respect of their current consumption, they differ in that, in the case of “switch drive”, current is consumed in centralized fashion by gradation amplifiers of the same number (for example 64) as the number of voltage gradations, whereas, in the case of “amplifier drive”, current is consumed in dispersed fashion by the same number of amplifiers as the number of output terminals (for example 396), which is considerably greater than the number of voltage gradations.
In the case of a data line drive circuit i.e. a circuit in which a plurality of data lines of a liquid-crystal panel are driven by simultaneously outputting a plurality of different gradation voltages from a plurality of output terminals, if “switch drive” is adopted, usually, the same number of gradation amplifiers as the number of gradations are provided. Also, typically, a plurality of different gradation voltages amplified (or buffered) by these gradation amplifiers are selected by the gradation voltage selection circuit and respectively supplied to the output terminals of the data line drive circuits. A technique for reducing current consumption in this case is to identify the gradation amplifiers that are employed and the gradation amplifiers that are not employed when the gradation voltages are outputted, and to disable the operation of the gradation amplifiers that are not employed. An example of this technique is disclosed in Japanese Unexamined Patent Application Publication No. 2002-108301.
FIG. 11 is a functional block diagram showing an example of a data line drive circuit corresponding to the circuit layout disclosed in Japanese Unexamined Patent Application Publication No. 2002-108301, in which no frame memory RAM is incorporated.
The data line drive circuit of FIG. 11 comprises a decision circuit 101, an enabling/disabling circuit 102, a gradation voltage generating circuit 103, a gradation amplifier circuit 104, a first data latch circuit 105, a second data latch circuit 106, a level shifting/decoding circuit 107, a gradation voltage selection circuit 108, and an output circuit 109. n output terminals S1 to Sn corresponding to then output lines are provided on the output side of the output circuit 109 (n is an integer of 2 or more).
The decision circuit 101 decides on the gradation to be used (i.e. the respective gradations of the n output lines corresponding to the input gradation data) on the n output lines in accordance with 6-bit digital gradation data that is input (on an interface) from an external CPU (central processing unit, not shown) and outputs the result of this decision in 64-bit form. The enabling/disabling circuit 102 determines whether the respective gradation is to be used or not in accordance with the 64-bit decision results data from the decision circuit 101 and delivers a 64-bit control signal in accordance with this result to the gradation amplifier circuit 104. On the other hand, the gradation voltage generating circuit 103 generates the same number of gradation voltages as the prescribed number of gradations (in this case, 64) and delivers these to the gradation amplifier circuit 104.
The gradation amplifier circuit 104 comprises 64 gradation amplifiers, of the same number as the number of gradations, and respectively amplifies (or buffers) the 64 different gradation voltages delivered from the gradation voltage generating circuit 103. The operation of these gradation amplifiers is controlled in accordance with a control signal delivered from the enabling/disabling circuit 102 and selectively disables the operation of gradation amplifiers corresponding to gradations that are determined not to be used. This enables current consumption to be reduced. The gradation amplifier circuit 104 outputs to the gradation voltage selection circuit 108 a analogue gradation voltage that is thus subjected to control as to whether the amplifier in question is to be used or not and which is amplified (or buffered).
The first data latch circuit 105 successively stores the 6-bit gradation data input from outside, in accordance with a latch signal LAT. The second data latch circuit 106 receives the gradation data of the n output lines stored in the first data latch circuit 105, in accordance with a horizontal signal STB, and holds the gradation data to output simultaneously onto the n output lines. For each of the n output lines, the level shifting/decoding circuit 107 performs level shift the 6-bit gradation data delivered from the second data latch circuit 106 and identifies the gradation that is to be selected by decoding thereof.
The gradation voltage selection circuit 108 inputs 64 analogue gradation voltages whose use or non-use is controlled, and which are amplified (or buffered) by 64 gradation amplifiers in the gradation amplifier circuit 104. For each of the n output lines, the gradation voltage selection circuit 108 selects a single analogue gradation voltage level from these 64 different analogue gradation voltage levels, in accordance with the identification result obtained from the level shifting+decoding circuit 107. The output circuit 109 respectively outputs the gradation voltage which is thus selected to the n output terminals S1 to Sn through the n output lines.
In the prior art data line drive circuit layout shown in FIG. 11, the power consumption can be reduced, but problems occur when RAM (Random Access Memory) that functions as a frame memory is added.
In a liquid-crystal display device, which is employed in appliances where a still image is often displayed, such as a mobile telephone, a frame memory is incorporated in the data line drive circuit. Reduction in power consumption is aimed at by arranging for the signal from the CPU to transfer image data only when the frame image is changed. The various signals delivered from the CPU and the various types of control signal of the data line drive circuit are therefore asynchronous. However, in order to display an image, the data line drive circuit must be driven with a fixed period. Also, when image data corresponding to one line are transferred from the frame memory to the first data latch circuit 105 that functions as a line memory, the image data corresponding to one line are transferred simultaneously using a latch signal of fixed period. Consequently, it is necessary to decide upon use/non-use of gradations in the image data in the line memory simultaneously.
Considering the case where the data line drive circuit FIG. 11 incorporates RAM that functions as a frame memory, this RAM must be arranged upstream of the first data latch circuit 105. Consequently, gradation data corresponding to one frame in the image data delivered from the CPU is first of all stored by being successively inputted to this RAM with a given timing. After this, data corresponding to one line of the gradation data is simultaneously transferred, with another timing, from this RAM to the first data latch circuit 105, where it is stored. Consequently, the problem arises that, even if the respective gradations to be used for the n output lines have been decided upon using the gradation data inputted to this RAM in the same way as was done in the case of the circuit layout shown in FIG. 11, the decision results do not necessarily agree with the gradations to be used by the gradation data outputted from this RAM (gradation data that was transferred and stored by the first data latch circuit 105).
Also, since the image to be displayed by the image unit is unchanged, when the image is displayed by using the gradation data corresponding to one line stored in this RAM, there is no actual input action to input gradation data itself to this RAM. Consequently, in the prior art construction, the problem arises that image display cannot be achieved unless a decision of use/non-use is made based on input of gradation data from outside.
Thus, with the prior art data line drive circuit shown in FIG. 11, it is not possible to cope with requirements for RAM incorporation as described above. An example of a technique for effecting improvement in this respect is disclosed in Japanese Unexamined Patent Application Publication No. 2004-271930 “Drive circuit for a display device” (applied for on the 10 Mar. 2003). FIG. 12 shows an example of the circuit layout of the data line drive circuit used in the drive circuit of the display device of Japanese Unexamined Patent Application Publication No. 2004-271930.
As shown in FIG. 12, this data line drive circuit has the same construction as the data line drive circuit of FIG. 11 except for the fact that RAM 110 that functions as a frame memory (used for storing the image data corresponding to a single frame) is inserted upstream of the first data latch circuit 105 and the fact that use/non-use of the each gradation is decided upon using 64-bit gradation voltage data decision circuit 101 from the gradation voltage selection circuit 108. Accordingly, in order to simplify the description, identical circuit elements are given the same reference symbols as in FIG. 11 and description relating thereto is omitted.
The RAM 110 stores an amount of 6-bit gradation data inputted from outside corresponding to one frame. The amount of gradation data corresponding to one line (corresponding to n output lines) of the amount of data corresponding to one frame that is stored in the RAM 110 is simultaneously transferred to the first latch circuit 105 in response to a latch signal LAT. This amount of gradation data corresponding to one line is held in the first latch circuit 105. Also, the gradation data corresponding to one line (corresponding to n output lines) that is held in the first data latch circuit 105 is transferred simultaneously to the second data latch circuit 106 in response to the horizontal signal STB and is held in the second data latch circuit 106. The holding of this gradation data by the second data latch circuit 106 is continued for a horizontal period (1 H).
It should be noted that the first data latch circuit 105 is provided for the purpose of arranging that in the case where a gradation data write signal to the RAM 110 delivered from the CPU and a latch signal LAT are delivered overlapping in time, writing to the RAM 110 is performed with priority.
The decision circuit 101 examines the 6-bit gradation data corresponding to one line in the gradation voltage selection circuit 108 and decides on gradations which are then selected (gradations to be used) and gradations that are not selected (gradations not to be used). This utilizes the fact that this gradation use/non-use decision function and the original gradation voltage selection function possessed by the gradation voltage selection circuit 108 have in common the decoding of the same 6-bit data to 64-bit data. The circuit layout shown in FIG. 13A to FIG. 13D is employed for realizing this gradation use/non-use decision function.
FIG. 13A to FIG. 13D are views showing an example of a circuit, specifically decision circuit 101, that decides upon use/non-use (selection/non-selection) of gradations, corresponding to a single display line (corresponding to n output lines). The circuit layout is the same for each of the n output lines, so in FIG. 13A to FIG. 13D only the portion relating to a single output terminal S1 is shown.
In the decision circuit 101 of the construction shown in FIG. 13A to FIG. 13D, in the gradation voltage selection circuit 108 having a typical construction, switches 205 for selecting the gradation to be used in accordance with the output of the level shifting/decoding circuit 107 are provided. Also, in order to make possible the decision of a selection/non-selection of the gradation, switches 202 are provided that control the connection/non-connection action with the output terminal S1 respectively on the output sides of the 64 gradation amplifiers 201. These gradation amplifiers 201 are of the same number as the number of gradations (these gradation amplifiers 201 are provided in the gradation amplifier circuit 104). The decision circuit 101 of FIG. 13A to FIG. 13D is further provided with: switches 203a for pre-charging the power source voltage VDD on the Vn line (output side line of the switches 202); switches 207a for dropping the potential of the Vn line from the power source potential VDD to the earth level GND; and switches 206 for preventing the decision action of use/non-use (selection/non-selection) of a gradation being influenced by the output terminals S1 to Sn.
The decision circuit 101 of the construction shown in FIG. 13A to FIG. 13D reads and decodes an amount corresponding to one line of gradation data in the RAM 110 in the condition of FIG. 13A and performs opening/closing control of the gradation selection switches 205 in accordance with the result thereof. If a gradation voltage amplified (buffered) by the gradation amplifier 201 of FIG. 13A is selected, the gradation selection switch 205 thereof is turned ON (closed); if the gradation voltage is not selected, the gradation selection switch 205 is turned OFF (opened). This is the normal action based on the gradation voltage selection function of the gradation voltage selection circuit 108.
When the 6-bit gradation data delivered from the RAM 110 is decoded to 64-bit gradation data, in other words when the horizontal signal STB becomes high level (H), as shown in FIG. 13B, the power source voltage pre-charging switch 203a is turned ON. In this way, the power source voltage VDD is pre-charged onto the line Vn (output side of the switch 202) and, as a result, the line Vn becomes VDD level.
Next, after the power source voltage pre-charging switch 203a has returned to OFF, the ground voltage application switch 207a is turned ON. If, at this time, the gradation selection switch 205 is turned ON (if the gradation in question is selected), as shown in FIG. 13C, the line Vn drops from the VDD level to the GND level. Conversely, if at this point the gradation selection switch 205 is turned OFF (the gradation in question is not selected), as shown in FIG. 13D, the line Vn is held at the VDD level.
Thus, if the corresponding gradation is selected, the Vn line (the output side of the gradation amplifier 201 and gradation selection/non-selection decision switch 202 i.e. the output end of the gradation amplifier circuit 104) becomes GND level and if the corresponding gradation is not selected, the Vn line becomes VDD level. It is thereby possible for the decision circuit 101 to decide on selection/non-selection of the each gradation at this time, by reading the voltage level of the n Vn lines in the gradation voltage selection circuit 108.
The enabling/disabling circuit 102 disables the operation of the unselected gradation amplifier 201 in accordance with the result of the decision by the decision circuit 101 which has thus been obtained. After this, when the gradation selection/non-selection decision switch 202 and the decision operation effect-preventing switch 206 are turned ON, the output of the 64 gradation amplifiers 201 is delivered to the output terminals S1 to Sn.
FIG. 14 is a timing chart showing the operation of the drive circuit FIG. 12. The operation of the decision circuit 101 constructed as shown in FIG. 13 may be described as follows with reference to this timing chart. In order to simplify the display, in FIG. 14, only the waveform related to the output terminal S1 is shown. Also, in FIG. 14, “1 H” indicates one horizontal synchronization period.
First of all, at the timing 1 in FIG. 14, the latch signal LAT is turned ON, and, in response thereto, the gradation data corresponding to one line in the image data that is stored in the RAM 110 that functions as a frame memory is transferred and stored in the data latch circuit 105. At this point, the gradation selection/non-selection decision switch 202 is turned ON, the power source voltage pre-charging switch 203a is turned OFF, the decision operation effect-preventing switch 206 is turned ON, the ground voltage application switch 207a is turned OFF, and, as a result, the output terminal S1 is at level 0.
At the next timing i.e. timing 2, all of the decision result signals that are output by the decision circuit 101 become high-level (H), irrespective of the image data. As a result, all of the switches 202 are turned OFF, so all of the gradation amplifiers 201 are put in an inactive condition. Also, in order that the voltage when the decision operation is executed should not be applied to the data lines (output terminals S1 to Sn) of the liquid-crystal display device, all of the switches 206 are turned OFF. The condition of the switches at this time time is shown in FIG. 13A.
At the next timing i.e. timing 3, the horizontal signal STB is turned ON, and, in response thereto, the gradation data corresponding to one line in the first data latch circuit 105 is transferred and stored in the second data latch circuit 106. Also, the level shifting/decoding circuit 107 reads gradation data corresponding to one line in the second data latch circuit 106 and selects a gradation in accordance therewith by using the switch 205. Specifically, the gradations to be employed in regard to the n respective output lines are selected and other gradations are put in non-selected condition. In addition, at this time, the switch 203a is turned ON and, as a result, the line Vn is pre-charged to the power source voltage VDD. The conditions of the switches at this time are as shown in FIG. 13B.
At the next timing i.e. timinig 4, the switch 203a is turned OFF, and the switch 207a is turned ON. As a result, the line Vn whose the gradation selection switch 205 that is turned ON (i.e. the output line whereof the gradation voltage delivered from the gradation amplifier 201 is decided to be “used”) is lowered from the power source voltage VDD to the ground level GND. The condition of the switches at this time is that shown in FIG. 13C.
On the other hand, the power source voltage VDD of lines Vn whose gradation selection switch 205 was turned OFF (i.e. output lines whereof gradation voltage delivered from the gradation amplifier 201 was decided to be “not used”) is held without alteration. The condition of the switches at this time-point is that shown in FIG. 13D.
At this timing 4, the voltage level of each 64 lines that are connected with the gradation amplifier circuit 104 may be held as “1”, in case that the Vn line is, for example, power source voltage VDD. The voltage levels of the 64 lines may be held as “0”, in case that the Vn lines is, for example, ground voltage GND . The decision circuit 101 may therefore be constituted by a latch circuit.
At the next timing i.e. timing 5, the switch 207a is turned OFF. At the next timing i.e. timing 6, the switch 206 is turned ON and the gradation amplifiers 201 are respectively connected with the output terminals S1 to Sn. At this time, the gradation amplifiers 201 are maintained in the inactive condition in accordance with the decision result from the decision circuit 101 or altered to the activated condition. The gradation voltages in accordance with the gradation data are thereby applied to each data line through the output terminals S1 to Sn.
In general, it is desirable that the voltage that is supplied to respective parts by the data line drive circuit for the liquid-crystal display device should be held as far as possible fixed, except when the voltage level fluctuates due to, for example, changeover of the operational condition. In view of this aspect, as described above, in the case of the data line drive circuit (incorporating RAM) of FIG. 12, it is necessary for the decision operation effect-preventing switch 206 to be put in the OFF condition during execution of the gradation selection/non-selection decision operation in a single horizontal synchronization period (1 H). During this condition, the output terminals S1 to Sn therefore assume a high impedance (Hi-Z) condition. Specifically, a high-impedance (Hi-Z) period is generated. As a result, the period during which a constant voltage is maintained is decreased by the extent of the Hi-Z period. In order to compensate for this decrease, it is necessary to raise the operating speed of these circuits by improving the drive capability of the gradation amplifiers 201 or gradation voltage selection circuit 108. Therefore, the current consumption increases and the area of the circuitry increases.
In the data line drive circuit of FIG. 12, during the decision action of gradation selection/non-selection, all of the output terminals S1 to Sn (where for example n=396) are inevitably put in the Hi-Z condition. During this action, the gradation voltages cannot therefore be applied to all of the pixels of the liquid-crystal panel. This means that the charging period in respect of the capacitance of the pixels of the liquid-crystal panel becomes shorter, thereby lowering picture quality. In order to avoid this, the need is produced to raise the operating rate by increasing the drive capacity of the gradation amplifiers 201 and/or gradation voltage selection circuit 108 by an amount corresponding to the shortening of the charging time in respect of the capacitances of the pixels of the liquid-crystal panel.
In this way, in the case of the data line drive circuit of FIG. 12, the data line drive circuit incorporates RAM 110, and reduction in current consumption is aimed at by disabling the operation of the gradation amplifiers 201 corresponding to the gradations that are not selected and corresponding to incorporation of the RAM 110. However, picture quality is thereby reduced.
It has now been discovered that in the conventional drive circuit, in order to prevent a lowering of picture quality, it is necessary to increase the operation speed of the gradation amplifiers and/or gradation voltage selection circuit; this is associated with an increase in current consumption or increase in area of the circuitry.